Chip Scale Package (CSP) is one of the latest developed chip package technologies. Products obtained by CSP generally have advantages such as small sizes, good electrical and thermal properties. Wafer-level CSP (WCSP) technology, one of the CSP technologies, includes following processes: packaging a wafer; performing a burn-in test to the wafer; removing unqualified portions; and dicing the wafer into a plurality of single CSP circuits.
A semiconductor device having a wafer-level CSP structure is disclosed in a Chinese patent publication No. CN1630029A. Referring to FIG. 1, the semiconductor device includes a semiconductor substrate 11 having a pad 12 formed thereon; a passivation layer 14 on the semiconductor substrate 11; an opening in the passivation layer 14 exposing the pad 12; a redistribution layer 16 formed on a portion of the passivation layer 14 and in the opening and being connected with the pad 12; a columnar electrode 17 on a portion of the redistribution layer 16 outside the opening region; an insulating layer 20 covering the redistribution layer 16 and a portion of the passivation layer 14, wherein a surface of the insulating layer 20 is flush with a surface of the columnar electrode 17; and a solder ball 21 on the columnar electrode 17.
However, in conventional semiconductor devices, a solder wall is prone to fall off a columnar electrode.